| 08:00 | Registration (8:00 AM~18:00 PM) Room: Convention Center Lobby, SHICC, Level 1 | ||||||||||
| 08:30 | T1 - From Circuits to Startups: Translating Innovation into Impact (Entrepreneurship Tutorial) Conference Room: 5B+5C, SHICC, Level 5 | T2 - AI-Enhanced Implementation of High-Efficiency Delta-Sigma ADCs Conference Room: 5H, SHICC, Level 5 | T5 - CoDeCAS: Co-designing Devices, Circuits, Systems and Algorithms for Uncertainty aware Multimodal Artificial Intelligence at the Edge Conference Room: Yangtze River Hall, SHICC, Level 5 | T6 - Power electronic circuits-based safety enhancement techniques for lithium-ion batteries Conference Room: 5F, SHICC, Level 5 | T7 - High-Throughput Neural Signal Acquisition: Hardware Implementation and Bio-Inspired Approaches Conference Room: 5A, SHICC, Level 5 | T8 - Advancing Spatial Intelligence —— Geometric Modeling, Representation Learning, and 3D Compression Conference Room: 5I, SHICC, Level 5 | T9 - From SNNs to Silicon: Automated hardware deployment of spiking neural networks Conference Room: 5D+5E, SHICC, Level 5 | T16 - Mm-Wave to THz Signal Generation in CMOS: An Injection Locking Approach Conference Room: 5J, SHICC, Level 5 | Standard Workshop Conference Room: 3A, SHICC, Level 3 | Workshop of the Cryo-Electronics for Quantum Systems and HPC (Cryo4QHPC) Special Interest Group Conference Room: 3D, SHICC, Level 3 | |
| 09:00 | |||||||||||
| 09:30 | |||||||||||
| 10:00 | Coffee Break Room: Convention Center Lobby, SHICC, Level 5 | ||||||||||
| 10:30 | T1 - From Circuits to Startups: Translating Innovation into Impact (Entrepreneurship Tutorial) Conference Room: 5B+5C, SHICC, Level 5 | T2 - AI-Enhanced Implementation of High-Efficiency Delta-Sigma ADCs Conference Room: 5H, SHICC, Level 5 | T5 - CoDeCAS: Co-designing Devices, Circuits, Systems and Algorithms for Uncertainty aware Multimodal Artificial Intelligence at the Edge Conference Room: Yangtze River Hall, SHICC, Level 5 | T6 - Power electronic circuits-based safety enhancement techniques for lithium-ion batteries Conference Room: 5F, SHICC, Level 5 | T7 - High-Throughput Neural Signal Acquisition: Hardware Implementation and Bio-Inspired Approaches Conference Room: 5A, SHICC, Level 5 | T8 - Advancing Spatial Intelligence —— Geometric Modeling, Representation Learning, and 3D Compression Conference Room: 5I, SHICC, Level 5 | T9 - From SNNs to Silicon: Automated hardware deployment of spiking neural networks Conference Room: 5D+5E, SHICC, Level 5 | T16 - Mm-Wave to THz Signal Generation in CMOS: An Injection Locking Approach Conference Room: 5J, SHICC, Level 5 | Standard Workshop Conference Room: 3A, SHICC, Level 3 | ||
| 11:00 | |||||||||||
| 11:30 | |||||||||||
| 12:00 | Lunch | ||||||||||
| 12:30 | |||||||||||
| 13:00 | |||||||||||
| 13:30 | T17 - Efficient Learning-based Models for Multimodal Data Compression Conference Room: 5B+5C, SHICC, Level 5 | T13 - Optical Biotelemetry Systems: Basics and Advances for Wireless Data and Power Transmission in Biomedical Implants Conference Room: 5H, SHICC, Level 5 | T11 - Visual Signal Processing from Human to Embodied Intelligence Conference Room: Yangtze River Hall, SHICC, Level 5 | T4 - Towards 6G UWB Signal Processing Chain Design Conference Room: 5F, SHICC, Level 5 | T15 - Modern Power Amplifier Design: From Classical Principles to AI-Assisted Optimization Conference Room: 5A, SHICC, Level 5 | T12 - Intelligent Design of Wireless Power Transfer: From Fundamentals to AI-Driven Frameworks Conference Room: 5I, SHICC, Level 5 | T10 - Low-voltage frequency generation, modulation, and demodulation circuits for mobile IoT Conference Room: 5D+5E, SHICC, Level 5 | T14 - Leveraging IEEE DataPort and IEEE Data Descriptions for Enhanced Research Impact and Student Engagement Conference Room: 5J, SHICC, Level 5 | Standard Workshop Conference Room: 3A, SHICC, Level 3 | CASS-CONNECT: Connecting Academia and Industry Workshop Conference Room: 3B, SHICC, Level 3 | |
| 14:00 | Workshop of the Cryo-Electronics for Quantum Systems and HPC (Cryo4QHPC) Special Interest Group Conference Room: 3D, SHICC, Level 3 | ||||||||||
| 14:30 | |||||||||||
| 15:00 | Coffee Break Room: Convention Center Lobby, SHICC, Level 5 | ||||||||||
| 15:30 | T17 - Efficient Learning-based Models for Multimodal Data Compression Conference Room: 5B+5C, SHICC, Level 5 | T13 - Optical Biotelemetry Systems: Basics and Advances for Wireless Data and Power Transmission in Biomedical Implants Conference Room: 5H, SHICC, Level 5 | T11 - Visual Signal Processing from Human to Embodied Intelligence Conference Room: Yangtze River Hall, SHICC, Level 5 | T4 - Towards 6G UWB Signal Processing Chain Design Conference Room: 5F, SHICC, Level 5 | T15 - Modern Power Amplifier Design: From Classical Principles to AI-Assisted Optimization Conference Room: 5A, SHICC, Level 5 | T12 - Intelligent Design of Wireless Power Transfer: From Fundamentals to AI-Driven Frameworks Conference Room: 5I, SHICC, Level 5 | T10 - Low-voltage frequency generation, modulation, and demodulation circuits for mobile IoT Conference Room: 5D+5E, SHICC, Level 5 | T14 - Leveraging IEEE DataPort and IEEE Data Descriptions for Enhanced Research Impact and Student Engagement Conference Room: 5J, SHICC, Level 5 | Standard Workshop Conference Room: 3A, SHICC, Level 3 | ||
| 16:00 | |||||||||||
| 16:30 | |||||||||||
| 17:00 | |||||||||||
| 17:30 | |||||||||||
| 18:00 | Welcome Reception Room: Pearl Hall & Foyer, Shanghai Min, SHICC, Level 7 | ||||||||||
| 21:00 | |||||||||||
| 08:00 | Registration (8:00 AM~18:00 PM) Room: Convention Center Lobby, SHICC, Level 1 | |||||||||||||||||
| 08:30 | Opening Ceremony Conference Room: Grand Ballroom 1, SHICC, Level 7 | |||||||||||||||||
| 09:00 | Keynote: New Semiconductor Path in Practice Conference Room: Grand Ballroom 1, SHICC, Level 7 | |||||||||||||||||
| 09:30 | ||||||||||||||||||
| 10:00 | Coffee Break Room: Grand Ballroom 1 Foyer, SHICC, Level 7/Exhibition Area & Poster Gallery, SHICC, Level 3 | Poster Session & Live Demo Room: SHICC Lobby, Level 3 | ||||||||||||||||
| 10:30 | Modeling, Sensors, and Emerging Analog Systems Conference Room: 3C, SHICC, Level 3 | High-Speed Data Converters and Time-Domain ADCs Conference Room: 3I+3J, SHICC, Level 3 | High-Speed Interface and Wireline Circuits Conference Room: 3A, SHICC, Level 3 | Hardware Security for Internet-of-Things, Cyber-Physical Systems I Conference Room: 3D, SHICC, Level 3 | SoC, NoC, Multi-Core, and 3D/2.5D Integrated Circuits and Systems I Conference Room: 3E, SHICC, Level 3 | Post-Quantum Cryptography and High-Speed Links Conference Room: 3B, SHICC, Level 3 | Integrated Power Circuits and Charge Pumps Conference Room: 3G, SHICC, Level 3 | Ferroelectric and Memristive in-Memory Computing Conference Room: 5C, SHICC, Level 5 | Spiking Neural Network Architectures and Learning Conference Room: 5F, SHICC, Level 5 | Image and Vision Sensors I Conference Room: 5D, SHICC, Level 5 | Accelerators for Machine Learning Conference Room: 5H, SHICC, Level 5 | Representation and Compression for Vision and Multimodal Learning Systems Conference Room: 5E, SHICC, Level 5 | Synergies between Emerging AI Technologies and Circuits and Systems Conference Room: 5A, SHICC, Level 5 | AI for Medical Signal and Image Analysis Conference Room: 5B, SHICC, Level 5 | ||||
| 11:00 | ||||||||||||||||||
| 11:30 | ||||||||||||||||||
| 12:00 | Lunch Room: Mandarin Hall, SHICC, Level 1 | |||||||||||||||||
| 12:30 | ||||||||||||||||||
| 13:00 | ||||||||||||||||||
| 13:30 | Keynote: Unprecedented Vision - From Single photon Detectors and Pixels to Engineering and Health Systems Conference Room: Grand Ballroom 1, SHICC, Level 7 | |||||||||||||||||
| 14:00 | ||||||||||||||||||
| 14:30 | Coffee Break Room: Exhibition Area & Poster Gallery, SHICC, Level 3 | Poster Session Room: SHICC Lobby, Level 3 | ||||||||||||||||
| 15:00 | AI-Assisted and Emerging Analog Circuits Conference Room: 3C, SHICC, Level 3 | Pipeline and Non-Conventional ADC Architectures Conference Room: 3I+3J, SHICC, Level 3 | Voltage References and Power Management Conference Room: 3A, SHICC, Level 3 | Datapath & Arithmetic Circuits and Systems I Conference Room: 3D, SHICC, Level 3 | SoC, NoC, Multi-Core, and 3D/2.5D Integrated Circuits and Systems II Conference Room: 3E, SHICC, Level 3 | Wireless Communications I Conference Room: 3B, SHICC, Level 3 | High Efficiency Converters and Drive Circuits for Specialized Applications Conference Room: 3G, SHICC, Level 3 | Spintronics-based In-Memory Computing Conference Room: 5C, SHICC, Level 5 | Neuromorphic Circuits and Neuron Implementations Conference Room: 5F, SHICC, Level 5 | Biochemical and Environmental Sensors Conference Room: 5D, SHICC, Level 5 | Circuits, Systems and Architectures for Machine Learning I Conference Room: 5H, SHICC, Level 5 | Architectures and Compression Techniques for Rendering, Perception, and Forecasting Conference Room: 5E, SHICC, Level 5 | Artificial Intelligence in Power and Energy Circuits and Systems I Conference Room: 5A, SHICC, Level 5 | Bio-Signal Acquisition Front-Ends Conference Room: 5B, SHICC, Level 5 | IEEE CASS Student Design Competition Conference Room: Yangtze River Hall, SHICC, Level 5 | Artificial Intelligence Workshop: Foundation Models, Compute Platforms, and Emerging Application Conference Room: 5J, SHICC, Level 5 | ||
| 15:30 | ||||||||||||||||||
| 16:00 | ||||||||||||||||||
| 16:30 | Programmable, High-Drive, and High-Voltage Amplifiers Conference Room: 3C, SHICC, Level 3 | Delta–Sigma ADCs and DAC Techniques Conference Room: 3I+3J, SHICC, Level 3 | VCO Design and Oscillator Techniques Conference Room: 3A, SHICC, Level 3 | Datapath & Arithmetic Circuits and Systems II Conference Room: 3D, SHICC, Level 3 | Electronic Design Automation and Physical Design I Conference Room: 3E, SHICC, Level 3 | Wireless Communications II Conference Room: 3B, SHICC, Level 3 | Circuits and Systems for Wireless Power Transfer applications Conference Room: 3G, SHICC, Level 3 | Quantum Computing I Conference Room: 5C, SHICC, Level 5 | Grand Challenge on Neural Network-based Video Coding Conference Room: 5F, SHICC, Level 5 | Sensory Circuits and Systems I Conference Room: 5D, SHICC, Level 5 | Circuits, Systems and Architectures for Machine Learning II Conference Room: 5H, SHICC, Level 5 | Multimodal Dialog, Speech Processing, and 3D Representation Conference Room: 5E, SHICC, Level 5 | Artificial Intelligence in Power and Energy Circuits and Systems II Conference Room: 5A, SHICC, Level 5 | Medical Computing Hardware and SoCs Conference Room: 5B, SHICC, Level 5 | IEEE CASS Mentoring Program Conference Room: Yangtze River Hall, SHICC, Level 5 | |||
| 17:00 | ||||||||||||||||||
| 17:30 | ||||||||||||||||||
| 18:00-21:30 | WiCAS-YPCAS Event Room: Europe Hall, SHICC, Level 5 | |||||||||||||||||
| 08:00 | Registration (8:00 AM~18:00 PM) Room: Convention Center Lobby, SHICC, Level 1 | |||||||||||||||||
| 08:00 | Kirchhoff and IEEE CASS Awards Conference Room: Grand Ballroom 1, SHICC, Level 7 | |||||||||||||||||
| 08:30 | ||||||||||||||||||
| 09:00 | Keynote: Quantum Network: Quantum Communication, Computation, and Metrology Conference Room: Grand Ballroom 1, SHICC, Level 7 | |||||||||||||||||
| 09:30 | ||||||||||||||||||
| 10:00 | Coffee Break Room: Exhibition Area & Poster Gallery, SHICC, Level 3 | Poster Session & Live Demo Room: SHICC Lobby, Level 3 | ||||||||||||||||
| 10:30 | RF Frequency Generation and Synthesizers Conference Room: 3C, SHICC, Level 3 | Time-Interleaved and High-Speed SAR ADCs Conference Room: 3I+3J, SHICC, Level 3 | Oscillators, PLLs, and Clock Generation Conference Room: 3A, SHICC, Level 3 | Hardware Security for Logic, Circuits and Architectures I Conference Room: 3D, SHICC, Level 3 | Electronic Design Automation and Physical Design II Conference Room: 3E, SHICC, Level 3 | Wireline Communications I Conference Room: 3B, SHICC, Level 3 | Circuits and Systems for Enhanced DC-DC Switch-mode Power Supplies Conference Room: 3G, SHICC, Level 3 | AI Circuits and Architectures Conference Room: 5C, SHICC, Level 5 | Compute-in-Memory-Based Neural Computing Conference Room: 5F, SHICC, Level 5 | Sensory Signal Conditioning Conference Room: 5D, SHICC, Level 5 | Quantization, Approximation, and Compression for ML Hardware I Conference Room: 5H, SHICC, Level 5 | Multimodal Interfaces and Efficient Architectures for Intelligent Visual Systems Conference Room: 5E, SHICC, Level 5 | Empowering the Evolving Electrical Grid: Circuits & Systems for Greener Generation, Distribution I Conference Room: 5A, SHICC, Level 5 | Neural Recording and Stimulation ASICs Conference Room: 5B, SHICC, Level 5 | ||||
| 11:00 | ||||||||||||||||||
| 11:30 | ||||||||||||||||||
| 12:00 | Lunch Room: Mandarin Hall, SHICC, Level 1 | |||||||||||||||||
| 12:30 | ||||||||||||||||||
| 13:00 | ||||||||||||||||||
| 13:30 | Keynote: Taming the Dragon: Circuits and Systems for Energy-efficient and Secure Computation Conference Room: Grand Ballroom 1, SHICC, Level 7 | |||||||||||||||||
| 14:00 | IEEE CASS Chapter Leadership Workshop @ ISCAS 2026 (Shanghai) Conference Room: 5I, SHICC, Level 5 | |||||||||||||||||
| 14:30 | Coffee Break Room: Exhibition Area & Poster Gallery, SHICC, Level 3 | Poster Session Room: SHICC Lobby, Level 3 | ||||||||||||||||
| 15:00 | RF and mm-Wave Low-Noise Amplifiers Conference Room: 3C, SHICC, Level 3 | Delta–Sigma and Zoom ADCs Conference Room: 3I+3J, SHICC, Level 3 | Multiphase PLLs and Injection-Locked Clocks Conference Room: 3A, SHICC, Level 3 | Hardware Security for Logic, Circuits and Architectures II Conference Room: 3D, SHICC, Level 3 | Electronic Design Automation and Physical Design III Conference Room: 3E, SHICC, Level 3 | Homomorphic Encryption and Quantum Circuits Conference Room: 3B, SHICC, Level 3 | Circuits & Systems for Energy Harvesting I Conference Room: 3G, SHICC, Level 3 | Nanoelectronic Circuits Conference Room: 5C, SHICC, Level 5 | Neuromorphic Processor Architecture and System Conference Room: 5F, SHICC, Level 5 | Machine Learning for Signal Processing Conference Room: 5D, SHICC, Level 5 | Compute-in-Memory I Conference Room: 5H, SHICC, Level 5 | Computational Intelligence for Multimedia Understanding Conference Room: 5E, SHICC, Level 5 | Empowering the Evolving Electrical Grid: Circuits & Systems for Greener Generation, Distribution II Conference Room: 5A, SHICC, Level 5 | Sensing Interfaces and SoCs Conference Room: 5B, SHICC, Level 5 | Industry Forum I: AI-Driven Innovation for the Future Chip Design Conference Room: Grand Ballroom 1, SHICC, Level 7 | Industry Forum II: Charting the Next Era of Semiconductors Conference Room: Yellow River, SHICC, Level 3 | ||
| 15:30 | ||||||||||||||||||
| 16:00 | ||||||||||||||||||
| 16:30 | RF and mm-Wave Transceivers and Receivers Conference Room: 3C, SHICC, Level 3 | Noise-Shaping ADCs and DAC Techniques for SAR ADCs Conference Room: 3I+3J, SHICC, Level 3 | VCO Design and Oscillator Techniques Conference Room: 3A, SHICC, Level 3 | Hardware Security for Logic, Circuits and Architectures III Conference Room: 3D, SHICC, Level 3 | Programmable, Reconfigurable & Array Architectures I Conference Room: 3E, SHICC, Level 3 | AI/ML for Communication and Signal Processing Conference Room: 3B, SHICC, Level 3 | Circuits & Systems for Energy Harvesting II Conference Room: 3G, SHICC, Level 3 | Quantum Computing II Conference Room: 5C, SHICC, Level 5 | Neuromorphic Learning and Plasticity Conference Room: 5F, SHICC, Level 5 | Signal Processing Theories and Algorithms for Biosignals Conference Room: 5D, SHICC, Level 5 | Compute-in-Memory II Conference Room: 5H, SHICC, Level 5 | Circuits and Systems for Coding and Processing Conference Room: 5E, SHICC, Level 5 | Specialized Hardware for Embodied AI Application and Neuromorphic Computing I Conference Room: 5A, SHICC, Level 5 | Wireless Power and Implantable Systems Conference Room: 5B, SHICC, Level 5 | ||||
| 17:00 | ||||||||||||||||||
| 17:30 | ||||||||||||||||||
| 18:00 | ||||||||||||||||||
| 19:00 | Gala Dinner & ISCAS Awards Ceremony Conference Room: Grand Ballroom 1, SHICC, Level 7 | |||||||||||||||||
| 21:00 | ||||||||||||||||||
| 08:30 | Registration (8:30 AM~13:00 PM) Room: Convention Center Lobby, SHICC, Level 1 | ||||||||||||||
| 09:00 | Keynote: From Memory-Constrained to Memory-Optimized: How Engram Conditional Memory + MRDIMM/CXL Reshapes Sparse AI Architectures Conference Room: Grand Ballroom 1, SHICC, Level 7 | ||||||||||||||
| 09:30 | |||||||||||||||
| 10:00 | Coffee Break Room: Exhibition Area & Poster Gallery, SHICC, Level 3 | Poster Session Room: SHICC Lobby, Level 3 | |||||||||||||
| 10:30 | RF and mm-Wave Power Amplifiers and Combiner Conference Room: 3C, SHICC, Level 3 | SAR ADC Calibration and Energy Optimization Conference Room: 3I+3J, SHICC, Level 3 | Advanced Analog and Mixed-Signal Techniques II Conference Room: 3A, SHICC, Level 3 | Low-Power Logic, Circuits & Architectures I Conference Room: 3D, SHICC, Level 3 | Design and Verification of Digital Integrated Circuits and Systems I Conference Room: 3E, SHICC, Level 3 | CAS Education and Outreach and the Open Silicon Initiative Conference Room: 3B, SHICC, Level 3 | Modeling, Control, and Power Management Conference Room: 3G, SHICC, Level 3 | WF-IoT Conference Room: 5C, SHICC, Level 5 | Hardware-Aware Neural Networks Conference Room: 5F, SHICC, Level 5 | Image Processing: Segmentation, Compression, Restoration, Registration, and Enhancement Conference Room: 5D, SHICC, Level 5 | Conventional and Emerging Memory Circuits and Architectures Conference Room: 5H, SHICC, Level 5 | Video Coding Conference Room: 5E, SHICC, Level 5 | Specialized Hardware for Embodied AI Application and Neuromorphic Computing II Conference Room: 5A, SHICC, Level 5 | Flexible Electronics Conference Room: 5B, SHICC, Level 5 | |
| 11:00 | |||||||||||||||
| 11:30 | |||||||||||||||
| 12:00 | Lunch Room: Mandarin Hall, SHICC, Level 1 | ||||||||||||||
| 12:30 | |||||||||||||||
| 13:00 | |||||||||||||||
| 13:30 | RF Switches, Couplers, and Phase Control Conference Room: 3C, SHICC, Level 3 | Precision and Low-Noise Amplifiers Conference Room: 3I+3J, SHICC, Level 3 | Modeling Methods for Nonlinear Circuits and Systems I Conference Room: 3A, SHICC, Level 3 | Low-Power Logic, Circuits & Architectures II Conference Room: 3D, SHICC, Level 3 | Design and Verification of Digital Integrated Circuits and Systems II Conference Room: 3E, SHICC, Level 3 | Breaking Barriers in Privacy-Preserving Machine Learning: From Algorithms to Accelerators Conference Room: 3B, SHICC, Level 3 | Bridging Algorithms, Circuits, and Systems: Foundations and Applications of Artificial Intelligence Conference Room: 3G, SHICC, Level 3 | Energy-Efficient & High-Resolution Data Converters for Next-Generation Biomedical & Neural Interface Conference Room: 5C, SHICC, Level 5 | Neuromorphic Perception and Control Conference Room: 5F, SHICC, Level 5 | Image Processing: AI in Circuits and Systems Conference Room: 5D, SHICC, Level 5 | Edge Computing Conference Room: 5H, SHICC, Level 5 | Learning-based Image/Video Coding Conference Room: 5E, SHICC, Level 5 | Analysis and Optimization of Complex Systems and Artificial Intelligence Applications I Conference Room: 5A, SHICC, Level 5 | ||
| 14:00 | |||||||||||||||
| 14:30 | Poster Session Room: SHICC Lobby, Level 3 | ||||||||||||||
| 15:00 | Coffee Break Room: Exhibition Area & Poster Gallery, SHICC, Level 3 | ||||||||||||||
| 16:00 | Advanced Circuits and Systems for High-Speed Data Links and Wireless Connectivity Conference Room: 3A, SHICC, Level 3 | Low-Power Logic, Circuits & Architectures III Conference Room: 3D, SHICC, Level 3 | Circuits and Systems for Physiological Sign Detection and Risk Warning in the Elderly Conference Room: 3E, SHICC, Level 3 | Cross-Layer Innovation in Computer-in-Memory Chips Conference Room: 3B, SHICC, Level 3 | Application-Specific Computer Arithmetic for Post-Quantum Cryptography & Homomorphic Encryption Access Conference Room: 3G, SHICC, Level 3 | Integrated Circuits and Systems for Intelligent Edge and Biomedical Applications Conference Room: 5C, SHICC, Level 5 | Quantization, Approximation, and Compression for ML Hardware II Conference Room: 5F, SHICC, Level 5 | Compressive Sensing and Sparse Signal Processing Conference Room: 5D, SHICC, Level 5 | Cross-Layer Optimization for Machine Learning Conference Room: 5H, SHICC, Level 5 | Volumetric video coding and communication Conference Room: 5E, SHICC, Level 5 | Analysis and Optimization of Complex Systems and Artificial Intelligence Applications II Conference Room: 5A, SHICC, Level 5 | ||||
| 16:30 | |||||||||||||||
| 17:00 | |||||||||||||||
| 17:30 | |||||||||||||||
| 18:00 | Farewell Reception: Huangpu River Cruise 17:40 Group Departure from Venue (10-min walk) 18:30 Cruise Departure Location: Oriental Pearl Tourism Wharf | ||||||||||||||
| 20:30 | |||||||||||||||