Invited Speaker #1: Cheng Wang

Professor, School of Electronic Science and Engineering, University of Electronic Science and Technology, Chengdu, China

Title

Exploring the Noise Limit of Cryogenic Silicon Reflectometry for Quantum State Discrimination

Abstract

Quantum state discrimination dominates the cycle of quantum error correction. The fidelity and integration time are limited by the noise temperature of RF reflectometers. This talk introduces the recent progress of ultra-low noise cryogenic CMOS readout circuits from integrated physics group (IPG) in UESTC, including 4 aspects: gm-boosting low noise amplifier (LNA), noise canceling LNA, degenerated parametric amplifier (DPA) and mixer-first reflectometer. All of these works have achieved the state-of-the-art noise performance, pushing the boundary of quantum state readout.

Biography

Cheng Wang is a Professor in the School of Electronic Science and Engineering, University of Electronic Science and Technology (UESTC). He received the B.E. degree from Tsinghua University in 2008 and the Ph.D. degree from Massachusetts Institute of Technology (MIT) in 2020. His research spans cryogenic circuits for quantum sensing and control, molecular spectroscopy and clock, and terahertz phased array. He has received awards including the 2024 Sichuan Youth May Fourth Medal, recognition as “35 innovators under 35” (China) by MIT Technology Review, the IEEE SSCS Predoctoral Achievement Award, and the MIT MTL Doctoral Dissertation Seminar Award. As TPC chair, he hosted IEEE IMWS-AMP 2023 and RFIT 2024.

Invited Speaker #2: Xufeng Kou

Professor and Executive Dean, School of Information Science and Technology, ShanghaiTech University, Shanghai, China

Title

Cryogenic CMOS - From Device Level Physics to Reliable Cryogenic IC Design

Abstract

Cryogenic CMOS (Cryo-CMOS) technology has emerged as a key paradigm to bypass the power and memory-wall bottlenecks in advanced semiconductor scaling, enabling steep subthreshold swings and minimized leakage currents. Nevertheless, complex physical phenomena such as dopant freeze-out and band-tail effects cause severe extrapolation inaccuracies and numerical instabilities in standard commercial compact models, thereby blocking robust cryogenic IC design. To resolve these bottlenecks, this talk proposes a generic, continuous compact modeling scheme calibrated from 300 K down to 4.2 K, and demonstrates its application in cryogenic-optimized device and circuit design.

Biography

Xufeng Kou is a Professor and Executive Dean of the School of Information Science and Technology at ShanghaiTech University. He received his BS degree from Zhejiang University and his MS and PhD degrees in Electrical Engineering from UCLA. Since February 2016, he has been with ShanghaiTech University. He has published book chapters and more than 90 peer-reviewed journal and conference papers, including Nature Electronics, Nature Materials, Nature Nanotechnology, Nature Communications, Physical Review Letters, and IEEE IEDM, with more than 7000 citations. His awards include the Qualcomm Innovation Fellowship, Chinese Outstanding Student Abroad Scholarship, Distinguished PhD Dissertation Award of UCLA, Shanghai May 4th Youth Medal, Shanghai 35U35 Award, and Shanghai Pudong Elite Researcher Award.

Invited Speaker #3: Yuhao Shu

Associate Professor, College of Integrated Circuits, Nanjing University of Aeronautics and Astronautics, China

Title

Energy-Efficient eDRAM-Based Cryogenic In-Memory Computing Accelerator

Abstract

This talk presents recent work on energy-efficient eDRAM-based cryogenic in-memory computing accelerators. Cryogenic CMOS provides opportunities to improve device and circuit behavior, while cooling overhead in cryogenic systems makes energy efficiency an important design objective. The talk first introduces an eDRAM-based cryogenic IMC accelerator that supports multiple operation modes through cryogenic-aware bitcell and readout schemes. It then discusses an extension toward multi-bit eDRAM-based analog cryogenic IMC for higher computing density. Together, these designs highlight the potential of eDRAM-based cryogenic IMC as an energy-efficient computing platform for data-intensive workloads.

Biography

Yuhao Shu is an Associate Professor at the College of Integrated Circuits, Nanjing University of Aeronautics and Astronautics, China. His research interests include cryogenic CMOS circuits, in-memory computing, and energy-efficient circuit and system design. He has completed more than 10 chip tape-outs and published 13 first-/corresponding-author papers in journals and conferences including IEEE JSSC, TCAS-I, and CICC.

Invited Speaker #4: Ran Cheng

Associate Professor, College of Integrated Circuits, Zhejiang University, Hangzhou, China

Title

Process Development of Low Temperature CMOS Technology for Low Temperature Digital And Analog Applications

Abstract

This work reports DTCO-assisted process development of low-temperature CMOS technology on a standard 55-nm foundry platform, spanning process engineering, library validation, processor-level evaluation, and reliability analysis. Methods for threshold-voltage modulation were evaluated among various CMOS platforms. For 55 nm process, doping engineering was implemented, enabling improved device electrostatics at 77 K. Based on wafer-level characterization and device models, a dedicated LT PDK and corresponding standard cell libraries are developed and experimentally validated. Improvement of logic gates delay and processor level power efficiency at 77 K were demonstrated. Variability and hot carrier issues were also discussed to complement the device-level study. The reported threshold-voltage modulation methodology establishes a practical route for realizing balanced PPAC of LT CMOS for high-speed and energy-efficient computing.

Biography

Ran Cheng received her B.Eng. and Ph.D. degrees in Electrical and Computer Engineering from the National University of Singapore. She is currently an Associate Professor with the College of Integrated Circuits, Zhejiang University, Hangzhou, China. Her research includes cryogenic CMOS, emerging memory, and logic-memory joint applications. She has published over 80 peer-reviewed papers and leads major research projects on low temperature CMOS and ferroelectric circuits supported by national and provincial funding agencies.

Invited Speaker #5: Sudipto Chakraborty

IBM Research, US

Title

Scientific talk Challenges and opportunities for development of ultra-low power scaled quantum computing systems

Biography

Sudipto Chakraborty received a B.Tech from IIT Kharagpur in 1998 and a Ph.D. from Georgia Tech in 2002. He was with Texas Instruments until 2016, where he designed low power IC for more than 10 product families in automotive, wireless, medical, and microcontrollers. Since 2017, he has led low power circuit design for next generation quantum computing applications at IBM Research using nanometer CMOS. He has authored or co-authored more than 90 papers, two books, and 95 US patents. He has served on TPCs including ISSCC, CICC, RFIC, and IMS, and is an IBM master inventor. He serves as an associate editor of TCAS-I, TCAS-II, CASS Magazine and as a distinguished lecturer in IEEE MTT-S, CASS and SSCS.

Invited Speaker #6: Elena Blokhina

Associate Professor, University College Dublin

Title

Milestones and Challenges in Cryo-CMOS for Quantum Computing & Next steps for the SIG

Biography

Elena Blokhina received the Habilitation à Diriger des Recherches in Electronic Engineering from Sorbonne Université, a PhD in Physical and Mathematical Sciences, and an MSc in Physics with highest honours from Saratov State University. Since 2007, she has been with University College Dublin, where she is currently an Associate Professor. She is a member of the Institute of Physics, a Senior Member of IEEE, and has held leadership roles within the IEEE Circuits and Systems Society and the IEEE Microwave Theory and Technology Society, including serving on the IEEE Circuits and Systems Society Board of Governors. She has chaired and organised international conferences and workshops associated with IEEE ISCAS, IEEE ICECS and ESSERC. Her research focuses on quantum computing, quantum information processing, quantum electronics, and on-chip classical and quantum information processing.

Invited Speaker #7: Hanjun Jiang

Professor and Vice Dean, School of Integrated Circuits, Tsinghua University, Beijing, China

Title

CO-LINK: Cryogenic Optical Link for Cryogenic High Performance Computing and Scalable Quantum Computing

Abstract

The cryogenic high performance computing is attracting substantial interest due to the promising performance of integrated circuits under low temperature and critical cooling requirements with increasing computing power consumption. Scalable quantum computing is another important scenario for cryogenic electronics. Both applications require high-bandwidth data links working in cryogenic environments and across different temperature domains. This talk reviews possible solutions for cryogenic data links and focuses on cryogenic optical data link technique. A 56 Gbps cryogenic optical data link design will be shown as a demonstration, including link architecture, data transceiving ASICs and preliminary experimental results.

Biography

Hanjun Jiang received the B.S. degree in electronic engineering from Tsinghua University in 2001 and the Ph.D. degree in electrical engineering from Iowa State University in 2005. From 2005 to 2006, he was with Texas Instruments. He has been with the School of Integrated Circuits at Tsinghua University since 2007, where he is currently a full professor and vice dean. His research focuses on low power integrated circuits and systems for emerging applications including biomedical micro-systems and quantum computing. He has authored and co-authored over 200 peer-reviewed papers, contributed to 3 books, and holds more than 40 patents. He has served in IEEE chapter, editorial, and distinguished lecturer roles.

Invited Speaker #8: Pau Escofet

Title

TBD

Biography

Pau Escofet is a PhD student specializing in Quantum Computing Architecture at the N3Cat group at Universitat Politècnica de Catalunya (UPC). He earned his Bachelor's Degree in Computer Science from UPC in 2022, including an exchange semester at ETH Zurich, and obtained a Master's Degree in Advanced Telecommunication Technologies from UPC in 2023. His PhD research focuses on scalable architectures for quantum computing, targeting systems that can support thousands or millions of qubits to achieve quantum advantage. He has received recognitions including the Best Computer Science Bachelor's Thesis award from FIB Alumni, Top 10 Computer Science students in Spain in Nova Talent's Nova 111 Student List, and the Best Chemistry High-School Thesis award from Universitat Ramon Llull.