- Date/Time: Tuesday, May 26, 2026, 15:00–18:15 (Shanghai time)
- Venue: Yellow River, SHICC, Level 3
Abstract
As semiconductor scaling approaches lithographic and fundamental atomic limits, the traditional paradigms of Moore’s Law and Dennard’s Law are losing their effectiveness. Without transistor shrinking as the primary lever, how can performance continue to scale? This remains one of the industry’s most critical open questions. In this forum, prominent local enterprises will present its latest architectural innovations and engineering practices in mobile SoCs and AI computing chips, followed by a panel discussion to explore a new sustainable scaling path for the next decade. We cordially invite you to join the conversation.
Agenda
| Time | Session | Speaker |
|---|---|---|
| 15:00–15:05 | Opening | Yong Lian, York University |
| 15:05–15:45 | Topic 1: Practices of SoC Design with Novel Architectures | Huang Yong, Huawei Fellow |
| 15:45–16:25 | Topic 2: Computing Chip Design: Engineering Choices and Trade-offs | Xia Jing, Huawei Fellow |
| 16:25–16:40 | Coffee Break | |
| 16:40–17:55 | Panel Discussion | Chair: Handel H. Jones & Heng Liao Six panelists |
| 17:55–18:10 | Q&A | |
| 18:10–18:15 | Session Closing |