| May 24th, Morning (8:30 A.M. ~ 12:00 A.M.) | |
|---|---|
| T1 | From Circuits to Startups: Translating Innovation into Impact (Entrepreneurship Tutorial) |
| T2 | AI-Enhanced Implementation of High-Efficiency Delta-Sigma ADCs |
| T3 | |
| T4 | Towards 6G UWB Signal Processing Chain Design |
| T5 | CoDeCAS: Co-designing Devices, Circuits, Systems and Algorithms for Uncertainty aware Multimodal Artificial Intelligence at the Edge |
| T6 | Power electronic circuits-based safety enhancement techniques for lithium-ion batteries |
| T7 | High-Throughput Neural Signal Acquisition: Hardware Implementation and Bio-Inspired Approaches |
| T8 | Advancing Spatial Intelligence — Geometric Modeling, Representation Learning, and 3D Compression |
| T9 | From SNNs to Silicon: Automated hardware deployment of spiking neural networks |
| May 24th, Afternoon (13:30 P.M. ~ 17:00 P.M.) | |
| T10 | Low-voltage frequency generation, modulation, and demodulation circuits for mobile IoT |
| T11 | Visual Signal Processing from Human to Embodied Intelligence |
| T12 | Intelligent Design of Wireless Power Transfer: From Fundamentals to AI-Driven Frameworks |
| T13 | Optical Biotelemetry Systems: Basics and Advances for Wireless Data and Power Transmission in Biomedical Implants |
| T14 | Leveraging IEEE DataPort and IEEE Data Descriptions for Enhanced Research Impact and Student Engagement |
| T15 | Modern Power Amplifier Design: From Classical Principles to AI-Assisted Optimization |
| T16 | Mm-Wave to THz Signal Generation in CMOS: An Injection Locking Approach |
| T17 | Efficient Learning-based Models for Multimodal Data Compression |
Morning Session (8:30 A.M. ~ 12:00 A.M.)
T1 - From Circuits to Startups: Translating Innovation into Impact
Sunday | May 24, 2026 | 8:30 - 12:00
Abstract
This tutorial aims to equip researchers, engineers, and students in the circuits and systems (CAS) community with practical entrepreneurial skills to identify, validate, and subsequently translate technical innovation into real-world impact. While ISCAS provides a premier platform for advancing scientific and engineering knowledge, there is a growing need for guidance on identifying commercialization opportunities, developing sustainable business models, and navigating funding and startup ecosystems. The session will cover key aspects of technology entrepreneurship - including opportunity recognition, intellectual property strategy, market validation, and venture creation - illustrated through case studies relevant to circuits and systems innovations. Participants will gain not only foundational frameworks but also actionable insights to bridge the gap between research excellence and entrepreneurial success. The participants will also receive a checklist and relevant large language model (LLM) prompts.
Instructor(s)
- Jie Chen - Fudan University, China
- Michael Friebe - Professor, AGH University of Krakow, Poland
- Fakhrul Zaman Rokhani - Associate Professor, University of Minnesota, USA
Tentative Schedule
- 8:30 - 9:20: Opportunity recognition introduction
- 9:20 - 10:10: Intellectual property strategy introduction
- 10:10 - 10:30: Coffee break
- 10:30 - 11:20: Market validation introduction
- 11:20 - 12:00: Venture creation
Biography
Jie Chen: Jie Chen (M'99-SM'04-F'16) received his Ph.D. degree in Electrical and Computer Engineering from the University of Maryland, College Park, MD, USA. He is currently a Professor in the College of Biomedical Engineering at Fudan University, Shanghai, China, and a Professor in the Department of Electrical and Computer Engineering and an Adjunct Professor in the Department of Biomedical Engineering at the University of Alberta, Edmonton, AB, Canada. He has co-authored three books and more than 250 journal articles and conference proceedings (h-index: 50; citations: 10,500). Dr. Chen is a Fellow of the Canadian Academy of Engineering and the American Institute for Medical and Biological Engineering.
Michael Friebe: Professor, Faculty of Computer Science, AGH University of Krakow, Poland; Medical Faculty Otto-von-Guericke-University, Magdeburg, Germany; 5P Future of Health Investments, Bochum, Germany; https://www.friebelab.org/; member of the IEEE EMBS AdCom.
Fakhrul Zaman Rokhani: Fakhrul Zaman Rokhani received the Ph.D. degree from the University of Minnesota, USA. He is an associate professor at the Universiti Putra Malaysia and the deputy director of System-on-Chip Research Center of Excellence. He was with Intel Penang Design Center, ST Microelectronics, Huawei Technologies and Western Digital as visiting professor, visiting scholar at the ASIC & Systems State Key Lab at Fudan University, and a visiting professor at several other universities. His current research interests include low-power/energy-efficient system-on-chip (SoC) design and automation, IoT system integration, and sensors for food quality applications. In 2023, he co-founded a startup company focusing on low power IPs. He serves as Vice President of Education and Communications for IEEE CAS Society (2023-2026), steering committee of IEEE Future Direction - Global Semiconductors and Advance AI-Augmented Hardware Technologies and Systems (HART) at IEEE. On the publication front, he has been contributing as a Senior Associate Editor of TCAS-I, Associate Editor of the CAS Society newsletter, Guest Editor of TCAS-I and TCAS-II, and Technical Program/Publication Chair/Track chairs/Embedded Workshop Chair of several IEEE CASS conferences.
T2 - AI-Enhanced Implementation of High-Efficiency Delta-Sigma ADCs
Sunday | May 24, 2026 | 8:30 - 12:00
Abstract
High-efficiency oversampling analog-digital converters (ADCs) are still
at the forefront of integrated circuits and very popular when it comes
to research and development, both in industry and academia. While their
implementation as noise-shaping SAR ADCs comes with the drawback of
driving a large sampling capacitor merged with the capacitive DAC, the
delta sigma modulator (DSM) based converter omits this. Their
application range is huge, from wideband wireless communications to the
data acquisition in IoT sensor nodes that demands an ultra-high
resolution with very low power consumption. Due to the available high
integrator gain within the signal bandwidth and the feedback established
by the oversampling converters, they can achieve a relatively high
signal-to-noise-and-distortion ratio (SNDR) and
spurious-free-dynamic-range (SFDR), within the signal band of interest.
The ability to shape the unwanted noise and errors to the
out-of-the-band gains a substantial design degree of freedom to the
oversampling converters compared to their Nyquist counterparts. DSM is
found in two basic categories: Discrete-Time (DT) DSM with excellent
accuracy and also excellent power efficiency in recent dynamic
implementations. Continuous-Time (CT) DSM comes with important benefits
of inherent anti-aliasing filtering, easier drivability, and
power-efficient implementation due to the continuous-time signal
processing. Moreover, the architectural diversity of DSM has steadily
increased over the last decades, beyond others employing various kinds
of multi-stage designs, and incremental DSM have recently again gained
an increasing attention. Circuit designers should understand the
underlying trade-offs in detail before they can make the correct design
decisions.
This tutorial will provide a detailed review of the
fundamentals, important decision-making factors, recent trends and
advanced design techniques, and future perspectives on the
state-of-the-art oversampling delta-sigma converters, spanning a range
from DT to CT, free-running and incremental one. Moreover, regarding the
practical implementation, we will go through the classical methods,
covering the optimization-based loop-filter design, and then guide the
audience through the most recent advances of AI-based synthesis and
implementation of DSMs, both on systems and circuitry levels.
Instructor(s)
- Prof. Liang Qi - Shanghai Jiao Tong University, Shanghai, China
- Prof. José M. de la Rosa - University of Seville, Seville, Spain
Tentative Schedule
- 8:30 - 10:10: 1) The principle of delta-sigma ADC; 2) The implementation methodology: DT vs. CT; 3) Architectural choices; 4) Incremental operation
- 10:10 - 10:30: Coffee break
- 10:30 - 12:30: 1) An overview of classical loop-filter scaling method and automated design/optimization of DSMs; 2) Main practical aspects, pros and cons, of AI-assisted design; 3) Introduction to an AI-assisted DSM synthesis toolbox; 4) A comparison to other optimization methods
Biography
Liang Qi: Liang Qi (IEEE Senior Member) received Ph.D. degree from University of Macau, Macao, China, in 2019. He currently serves as an Associate Professor in School of Integrated Circuit, Shanghai Jiao Tong University (SJTU), Shanghai, China. Before he joined SJTU, he worked with Shanghai Hisilicon, where he conducted the project of multi-band (2G-5G) RX ADC. He was a Visiting Scholar at Ulm University, Germany, during the Ph.D. studies. His research interests include high-performance data converters and analog mixed-signal integrated circuits. Dr. Qi has served as an Associate Editor for the IEEE Transactions on Circuits and Systems - I: Regular Papers and IEEE Transactions on Circuits and Systems II: Express Briefs, respectively. He also is/has been a TPC Member for IEEE ESSERC, APCCAS, ICSICT, ICTA, and ASICON. He has received Outstanding Young Scholar Paper Award in IEEE ASICON 2021.
Jose M. de la Rosa: Jose M. de la Rosa (IEEE Fellow) received the M.S. degree in Physics in 1993 and the Ph.D. degree in Microelectronics in 2000, both from the University of Seville, Spain. He is a Full Professor at the Department of Electronics and Electromagnetism of the University of Seville. His main research interests are in analog and mixed-signal integrated circuits, especially high-performance sigma-delta data converters, including analysis, behavioral modeling, design, and design automation. He is an IEEE Fellow and has served in numerous editorial and leadership roles, including Editor-in-Chief of IEEE Transactions on Circuits and Systems II: Express Briefs (2020-2021) and Editor-in-Chief of IEEE Transactions on Circuits and Systems - I: Regular Papers.
T3 - Smarter Chips: AI for Hardware and Hardware for AI (cancelled)
T4 - Towards 6G UWB Signal Processing Chain Design
Sunday | May 24, 2026 | 8:30 - 12:00
Abstract
The evolution toward 6G networks is driven by the demand for extreme
bandwidth to support machine-type communications, holographic
experiences, and immersive reality. Achieving this requires
energy-efficient transceiver architectures capable of handling
ultra-wideband signals well beyond the limits of 5G. A central challenge
lies in data converters, where higher sampling rates lead to an increase
in both noise and power consumption.
This half-day tutorial,
“Towards 6G UWB Signal Processing Chain Design,” presents advances in
interleaved architectures and frequency-domain approaches based on Walsh
transformations. It covers the design of interleaved data converters,
Walsh-based transceivers, and AI-driven applications, including spectrum
sensing and interference mitigation. Participants will gain a
comprehensive understanding of the signal processing chain from core
principles to advanced circuit-level solutions, focusing on energy
efficiency, parallelization, and system-level performance.
Instructor(s)
- Dr. Abdel Martinez Alonso - Tech Idea Co., Ltd., Kanagawa, Japan
- Prof. Dr. Francois Rivet - IMS Laboratory, University of Bordeaux, Bordeaux, France
- Dr. Rodney Martinez Alonso - WaveCore Arenberg, KULEUVEN, Leuven, Belgium
Tentative Schedule
- 8:30 - 9:20: Introduction to Efficient Data Converters Design
- 9:20 - 10:10: Life beyond OFDM: Walsh domain encoding
- 10:10 - 10:30: Coffee break
- 10:30 - 12:00: From Theory to Impact: AI-Driven Applications of Walsh-Based Transceivers
Biography
Abdel Martinez Alonso: Dr. Abdel Martinez Alonso received his B.S. (2008) and M.S. (2012) degrees in Telecommunications and Electronics from the Polytechnic University Jose Antonio Echeverria, Havana, Cuba, and joined the LACETEL Research & Development Telecommunication Institute in 2008. Awarded the Monbukagakusho (MEXT) Scholarship in 2014, he earned a Ph.D. in Physical Electronics from the Tokyo Institute of Technology in 2018. He received the IEEE A-SSCC Distinguished Design Award in 2017 and was elevated to IEEE Senior Member in 2021. Since 2018, he has been a Senior Research Engineer at Tech Idea Co., Ltd., Kanagawa, Japan. His research interests include high-speed circuits and digitally assisted techniques for mixed-signal VLSI design and evaluation.
Francois Rivet: Prof. Dr. Francois Rivet received the Master's and Ph.D. degrees from the University of Bordeaux. He is tenured as an Associate Professor at Bordeaux INP and works in the IMS Laboratory, University of Bordeaux. He founded the Circuits and Systems research team in 2014. He has 160+ publications, 21 patents, and has served in major conference and project leadership roles, including General Chair of RFIC 2025 and coordinator of the EU HERMES project.
Rodney Martinez Alonso: Dr. Rodney Martinez Alonso obtained B.Sc. and M.Sc. degrees from the Havana University of Technology, later earned a Ph.D. from Ghent University in 2020, and is currently a Senior Postdoctoral Researcher at KU Leuven (FWO). His research focuses on AI applications for next-generation wireless systems, including AI-native autoencoders for Walsh-based ultrawideband communication within the HERMES project.
T5 - CoDeCAS: Co-designing Devices, Circuits, Systems and Algorithms for Uncertainty aware Multimodal Artificial Intelligence at the Edge
Sunday | May 24, 2026 | 8:30 - 12:00
Abstract
Uncertainty awareness in language and vision AI models are essential for robust decision making in critical real-time tasks at the Edge such as autonomous drone surveillance, and AR/VR-assisted healthcare. Model predictions often suffer from data, sensor and environmental imperfections leading to inaccurate decision making that is unacceptable in safety critical tasks. Various probabilistic AI techniques such as Monte-Carlo Dropout, Variational inference, Deep ensembles and Conformal predictions enable uncertainty awareness in the AI model predictions. However, challenges to deep learning inference at the Edge further aggravates with incorporation of prediction uncertainties due to multifold increase in compute and power requirements. We uniquely address these challenges all the way from novel device technology to circuits, architectures and co-designed algorithms, thus navigating the audience to the full stack research techniques and hardware/software co-design frameworks towards building sustainable as well as robust circuits and systems for modern AI processing.
Instructor(s)
- Amit Ranjan Trivedi - Associate Professor, University of Illinois at Chicago, IL, USA
- Priyesh Shukla - Assistant Professor, International Institute of Information Technology, Hyderabad, India
Tentative Schedule
- 8:30 - 9:00: Motivation of uncertainty-awareness in LLMs, SLMs, VLMs, CNNs from application case studies
- 9:00 - 9:30: Basics of uncertainty-aware (probabilistic) methods
- 9:30 - 10:10: Devices - Gaussian transistors and memtransistors for probabilistic ML
- 10:10 - 10:30: Coffee break
- 10:30 - 11:00: Circuits and architectures - Compute-in-Memory acceleration for probabilistic ML
- 11:00 - 11:30: Co-design with device/hardware characteristics and constraints
- 11:30 - 12:00: Impact on sustainable and robust edge systems, plus Q&A
Biography
Amit Ranjan Trivedi: Amit Ranjan Trivedi (Senior Member, IEEE) received the B.Tech. and M.Tech. degrees from IIT Kanpur and the Ph.D. from Georgia Tech. He is currently an Associate Professor at the University of Illinois at Chicago. He has authored/coauthored over 100 papers. His interests include machine learning at the edge, hardware security, and energy-efficient systems. He received the IEEE EDS Fellowship, NSF CAREER Award, and 2024 Intel Outstanding Researcher Award.
Priyesh Shukla: Priyesh Shukla (Member, IEEE) received the B.E. and M.E. degrees from BITS Pilani and the Ph.D. from UIC. He is currently an Assistant Professor at IIIT Hyderabad. His research interests include sustainable computing systems for AI and quantum computing. He is recipient of the 2019 Peter and Deborah Wexler award and AICAS 2022 best paper award.
T6 - Power electronic circuits-based safety enhancement techniques for lithium-ion batteries
Sunday | May 24, 2026 | 8:30 - 12:00
Abstract
Safety enhancement for lithium-ion batteries (LIBs) has received a lot of attention from academic and industrial fields. However, there is a lack of attention from the perspective of the application power electronics (PEs) in the systems. This tutorial gives a presentation about PE-based safety enhancement technologies for LIBs, mainly focusing on battery management. It introduces the latest advances in battery protection, balancing, monitoring, and lifetime improvement, all based on PE technologies. Detailed discussion and future research opportunities are given. This tutorial aims to provide a reference for PE researchers who want to make some efforts in LIB safety.
Instructor(s)
- Zhaoyang Zhao - Southwest Jiaotong University, Chengdu, China
- Herbert Ho-Ching Iu - The University of Western Australia, Crawley, WA, Australia
- Lizhou Liu - Sichuan University, Chengdu, China
Tentative Schedule
- 8:30 - 9:00: Introduction and overview
- 9:00 - 9:30: PE-based battery protection techniques
- 9:30 - 10:10: PE-based online monitoring techniques
- 10:10 - 10:30: Coffee break
- 10:30 - 11:00: PE-based lifetime improvement techniques
- 11:00 - 12:00: PE-based battery balancing techniques
Biography
Zhaoyang Zhao: Zhaoyang Zhao (Member, IEEE) received B.S. and M.S. degrees from Northeast Agricultural University and a Ph.D. from Chongqing University. He joined Southwest Jiaotong University in 2022 and is currently an Associate Professor with the Institute of Smart City and Intelligent Transportation. His research interests include condition monitoring, safety, and reliability of power electronic converters and battery systems.
Herbert Ho-Ching Iu: Herbert Ho-Ching Iu (Fellow, IEEE) received his B.Eng. from The University of Hong Kong and Ph.D. from The Hong Kong Polytechnic University. He is currently a Professor at The University of Western Australia. His research includes power electronics, renewable energy, nonlinear dynamics, and memristive systems. He serves in multiple IEEE editorial roles.
Lizhou Liu: Lizhou Liu (Member, IEEE) received B.S. and M.S. degrees from Southwest University of Science and Technology and a Ph.D. from Southwest Jiaotong University. He is currently an Associate Professor at Sichuan University. His research focuses on energy storage, especially battery voltage equalizers and hybrid energy storage.
T7 - High-Throughput Neural Signal Acquisition: Hardware Implementation and Bio-Inspired Approaches
Sunday | May 24, 2026 | 8:30 - 12:00
Abstract
This tutorial session explores cutting-edge advancements in neural signal sensing and neuromorphic engineering, with a focus on hardware implementation and bio-inspired design principles. The session will discuss the challenges and solutions for high-throughput neural signal wireless sensing, emphasizing circuit design methodologies and ultra-low-power implementations, as well as the evolution of neuromorphic engineering from strict brain mimicry to bio-inspired designs, with a vision for copy-and-paste approaches that map functional synaptic connectivity onto silicon circuits. This session will provide attendees with a comprehensive understanding of how hardware innovations are driving advancements in neural signal processing and neuromorphic systems, enabling applications in low-power computing, adaptive learning, and cognitive systems.
Instructor(s)
- Milin Zhang - Tsinghua University, Beijing, China
- Donhee Ham - Harvard University, USA
Tentative Schedule
- 8:30 - 10:10: Introduction to High-Throughput Wireless Neural Signal Sensing
- 10:10 - 10:30: Coffee break
- 10:30 - 12:00: Population-Scale Intracellular Recording and Biologically Grounded Neuromorphic Systems
Biography
Milin Zhang: Milin Zhang is an associate professor in Electronic Engineering at Tsinghua University. She received B.S. and M.S. degrees from Tsinghua and a Ph.D. from HKUST. She worked as a postdoctoral researcher at UPenn and joined Tsinghua in 2016. Her interests include smart sensors and biomedical interface circuits and systems.
Donhee Ham: Donhee Ham is the John A. and Elizabeth S. Armstrong Professor at Harvard University. He received his B.S. from Seoul National University and M.S./Ph.D. from Caltech. His research includes semiconductor-bio interfaces, bioelectronics, and machine intelligence. He is an IEEE Fellow and has served in leadership/editorial roles in SSCS and TBioCAS.
T8 - Advancing Spatial Intelligence —— Geometric Modeling, Representation Learning, and 3D Compression
Sunday | May 24, 2026 | 8:30 - 12:00
Abstract
3D spatial intelligence - the capacity to perceive, reason about, and manipulate geometric data - is increasingly vital for advancing artificial intelligence applications across various domains, including robotics, metaverse, immersive telepresence, and autonomous systems. This tutorial aims to provide a comprehensive overview of recent advancements in the field, covering critical aspects from geometric modeling to 3D representation learning and 3D compression (especially 3D Gaussian compression) techniques.
Instructor(s)
- Prof. Junhui Hou - City University of Hong Kong, Hong Kong SAR, China
- Prof. Weiyao Lin - Shanghai Jiao Tong University, China
Tentative Schedule
- 8:30 - 9:30: 3D Geometric Modeling and Representation
- 9:30 - 10:10: Augmented 3D Representation Learning with 2D Modalities/Structures
- 10:10 - 10:30: Coffee break
- 10:30 - 12:00: Compression of 3D Gaussian Representation
Biography
Junhui Hou: Dr. Junhui Hou is an Associate Professor with the Department of Computer Science, City University of Hong Kong. His interests include multidimensional visual computing such as light field, hyperspectral, geometry, and event data. He has served as Associate Editor for IEEE TIP, TVCG, TMM, and TCSVT and authored/co-authored 190+ papers.
Weiyao Lin: Weiyao Lin is a Distinguished Professor with Shanghai Jiao Tong University. He received his B.E. and M.E. from SJTU and Ph.D. from the University of Washington. He has authored/coauthored 100+ technical papers and holds 25 patents. His research includes multimedia processing and visual signal compression.
T9 - From SNNs to Silicon: Automated hardware deployment of spiking neural networks
Sunday | May 24, 2026 | 8:30 - 12:00
Abstract
Brain-inspired spiking neural networks promise 3–4 orders of magnitude
energy savings compared to conventional neural network implementations.
SNNs combine continuous neuron dynamics with discrete spike
communication, enabling rich temporal computation with efficient,
event-driven information transfer—these are among the key ingredients
allowing the human brain to operate on approximately 20
watts.
This tutorial provides an overview of unrolling SNNs
defined in a collection of simulators into FPGA bitstreams via a
customisable, open-source toolchain. We introduce a direct compilation
framework that translates SNN models into FPGA bitstreams: participants
will convert an existing spiking convolutional network to hardware, then
train and optimise their own architecture. Participants will learn to
program FPGA accelerators for SNNs and gain practical skills in mapping
conventional network architectures into the spiking domain. This
toolchain also serves as a stepping stone toward open-source
neuromorphic ASIC development.
Instructor(s)
- Michail Rontionov - University of Southampton, UK
- Dr. Jens Egholm Pedersen - Technical University of Denmark, DK
Tentative Schedule
- 8:30 - 9:20: Introduction to neuromorphic accelerators
- 9:20 - 10:10: Building and training quantized SNNs in JAX
- 10:10 - 10:30: Coffee break
- 10:30 - 11:00: Mapping NIR to FPGA with SpinalHDL
- 11:00 - 12:00: Hands-on running NIR networks on FPGA
Biography
Michail Rontionov: Michail Rontionov is a Ph.D. student supervised by David Thomas, focusing on computational theory at the software-hardware interface and neuromorphic computing. He completed an MSci with honours from Swansea University and has industry experience as an intern in Intel's HPC division.
Jens Egholm Pedersen: Dr. Pedersen received his Ph.D. in neuromorphic computing from KTH in 2025. He is a leading developer of the Neuromorphic Intermediate Representation bridging multiple neuromorphic platforms. He received the Misha Mahowald early career award and other fellowships, and chairs the Open Neuromorphic community.
Afternoon Session (13:30 P.M. ~ 17:00 P.M.)
T10 - Low-voltage frequency generation, modulation, and demodulation circuits for mobile IoT
Sunday | May 24, 2026 | 13:30 - 17:00
Abstract
As future wireless systems leveraging advanced CMOS technologies demand
not only low-power but also low-voltage design, robust frequency
generation, modulation and demodulation have become more critical than
ever. In particular, sub-0.5V frequency synthesis and modulation are
essential to enable battery-free operation in mobile IoT devices, as
they can be directly powered by energy harvesters without requiring
additional DC-DC converters. However, designing a low-voltage
fractional-N PLL is highly challenging, since both matching and
linearity degrade significantly as the supply voltage is scaled
down.
This half-day tutorial reviews the state-of-the-art PLL
architectures and presents fully voltage-mode PLL and transceiver
architectures that operate under a 0.5V supply voltage. In addition, the
extensive use of single-bit modulation and demodulation techniques for
the robust design of ultra-low-voltage transmitters and receivers will
be discussed.
Instructor(s)
- Prof. Woogeun Rhee - IEEE Fellow, Dept. of Semiconductor Convergence Engr., Sungkyunkwan University (SKKU), Suwon, Korea; Adjunct Chair Professor, School of Integrated Circuits, Tsinghua University, Beijing, China
Tentative Schedule
- 13:30 - 14:00: Introduction
- 14:00 - 14:30: Single-bit delta-sigma modulation for frequency generation and modulation
- 14:30 - 15:10: Voltage-mode hybrid fractional-N PLLs and transmitters
- 15:10 - 15:30: Coffee break
- 15:30 - 16:20: Low-voltage receivers
- 16:20 - 17:00: Design challenges and future considerations
Biography
Woogeun Rhee: Prof. Woogeun Rhee received B.S. from Seoul National University, M.S. from UCLA, and Ph.D. from UIUC. He worked at Conexant and IBM Watson, then served as Professor at Tsinghua University, and is currently with Sungkyunkwan University as Professor, while also serving as Adjunct Chair Professor at Tsinghua. He has published 180+ IEEE articles and holds 24 U.S. patents. His research focuses on energy-efficient short-range radios for mobile IoT, UWB transceivers, and mixed-signal circuits including PLLs. He is IEEE Fellow and serves as Editor-in-Chief of IEEE OJ-SSCS.
T11 - Visual Signal Processing from Human to Embodied Intelligence
Sunday | May 24, 2026 | 13:30 - 17:00
Abstract
This tutorial explores the cutting-edge intersection of human visual perception and embodied intelligence, bridging the gap between biological Human Visual System (HVS) and Robotic Visual System (RVS). We will examine how visual signal processing principles derived from human can be adapted and enhanced for embodied intelligence, such as image compression, restoration, and quality assessment, enabling more efficient embodied task execution. The tutorial covers fundamental concepts in visual perception, advanced signal processing techniques, and practical applications in embodied intelligence, with particular focus on how large language models can be integrated with visual processing for enhanced embodied capabilities.
Instructor(s)
- Chunyi Li - Center of AI Evaluation, Shanghai AI Laboratory, China
- Weisi Lin - Nanyang Technological University, Singapore
- Zicheng Zhang - Shanghai AI Lab, China
- Huiyu Duan - Shanghai Jiao Tong University, China
- Jianbo Zhang - Xinjiang University, China
- Guangtao Zhai - Shanghai Jiao Tong University, China
Tentative Schedule
- 13:30 - 14:20: Intelligence Visual Perception Loop
- 14:20 - 15:10: Traditional Visual Signal Processing for Human
- 15:10 - 15:30: Coffee break
- 15:30 - 17:00: Visual Signal Processing for Embodied Intelligence
Biography
Chunyi Li: Chunyi Li is the head of the embodied research group in the Center of AI Evaluation, Shanghai AI Laboratory. His research focuses on embodied large language models. He has published top-tier papers in IEEE TIP/CVPR/ICCV and serves as reviewer for journals including TPAMI, JSAC, TIP, TMM, and TCSVT.
Weisi Lin: Weisi Lin (IEEE Fellow) is President's Chair Professor and Associate Dean (Research) at NTU. He has published more than 200 journal articles and 230 conference papers, filed patents, and authored books. He has served as General Chair/TPC Chair for major IEEE conferences and as Associate Editor for several IEEE transactions.
Zicheng Zhang: Shanghai AI Lab, China. Homepage: https://zzc1998.github.io
Huiyu Duan: Shanghai Jiao Tong University, China. Homepage: https://duanhuiyu.github.io
Jianbo Zhang: Xinjiang University, China. Profile: https://scholar.google.com/citations?user=Eru2-TYAAAAJ
Guangtao Zhai: Shanghai Jiao Tong University, China. Profile: https://faculty.sjtu.edu.cn/zhaiguangtao/en/index.htm
T12 - Intelligent Design of Wireless Power Transfer: From Fundamentals to AI-Driven Frameworks
Sunday | May 24, 2026 | 13:30 - 17:00
Abstract
Wireless Power Transfer (WPT) has attracted significant attention as an
innovative technology enabling a wide range of applications, from
consumer electronics and electric vehicles to industrial robotics. The
development of efficient and reliable WPT systems, particularly in the
MHz frequency range, requires the integrated consideration of circuits,
magnetic coupling, electric-field coupling, and control. Conventional
design approaches, largely dependent on expert knowledge and
trial-and-error prototyping, face inherent limitations: they struggle to
address fundamental challenges such as output fluctuation and efficiency
degradation caused by load variation and coil misalignment, thereby
restricting scalability and innovation.
This tutorial will
provide both the fundamentals and the latest advancements in WPT, with a
special focus on methods that fundamentally overcome these challenges.
Beginning with the principles of inductive and electric-field
(capacitive) coupling, the tutorial will cover advanced load-independent
topologies and our uniquely developed AI-driven design methodologies,
characterized by fully numerical optimization, high-accuracy modeling,
and the integrated design of physical coil models with circuit component
values. Beyond serving as a powerful design tool, these approaches
represent a novel framework for principle-driven analysis and knowledge
discovery in WPT system design. Practical case studies, including
MHz-range GaN inverters and robotic applications, will demonstrate the
effectiveness of these methods. Future directions such as Simultaneous
Wireless Power and Data Transfer (SWPDT) will also be briefly discussed.
Instructor(s)
- Hiroo Sekiya - Chiba University, Japan
- Xiuqin Wei - Chiba Institute of Technology, Japan
Tentative Schedule
- 13:30 - 14:30: Fundamentals of Wireless Power Transfer
- 14:30 - 15:10: Advanced Load-Independent WPT Design
- 15:10 - 15:30: Coffee break
- 15:30 - 16:30: AI-Driven WPT Design Frameworks
- 16:30 - 17:00: Case Studies and Future Perspectives
Biography
Hiroo Sekiya: Hiroo Sekiya received the B.E., M.E., and Ph.D. degrees from Keio University and is currently a Professor at Chiba University. His interests include wireless power transfer, high-efficiency tuned amplifiers, resonant converters, nonlinear circuit phenomena, and AI-based design methodologies for power electronics. He has authored/co-authored over 480 papers and served the IEEE CASS community in multiple leadership and editorial roles.
Xiuqin Wei: Xiuqin Wei received the Ph.D. degree from Chiba University and is currently a Professor at Chiba Institute of Technology. Her interests include high-frequency/high-efficiency power inverters, AC-DC/DC-DC converters, and WPT systems. She has contributed extensively to resonant and load-independent topologies and serves in technical and editorial roles across IEEE and Japanese professional societies.
T13 - Optical Biotelemetry Systems: Basics and Advances for Wireless Data and Power Transmission in Biomedical Implants
Sunday | May 24, 2026 | 13:30 - 17:00
Abstract
This tutorial introduces to the design of wireless communication systems for biomedical implants by making a detailed focus on the basics and advances of the optical biotelemetry. In particular, the design of new architectures of biomedical systems is demanding to fulfill the need to acquire and process biological/neural signals providing high-quality healthcare to sick people. Therefore, the following key-points are required: design of novel biomedical apparatus for prosthetic devices, diagnostic and therapeutic instrumentations, neural systems, etc., as well as guaranteeing the capability to transmit-receive data from inside and outside of the human body by means of high-efficiency implantable wireless data link solutions. Therefore, it is needed to develop implantable (transcutaneous) wireless biotelemetry systems achieving high data rate transmission, high efficiency characteristics (low-voltage/low-power), small Si area and low Bit Error Ratio.
Instructor(s)
- Andrea De Marcellis - University of L'Aquila, L'Aquila, Italy
- Guido Di Patrizio Stanchieri - University of L'Aquila, L'Aquila, Italy
Tentative Schedule
- 13:30 - 14:00: Introduction to the biotelemetry
- 14:00 - 14:30: Wireless data link systems: an overview and the State-of-the-Art
- 14:30 - 15:10: Optical wireless biotelemetry system design: analog/digital CMOS electronic circuits
- 15:10 - 15:30: Coffee break
- 15:30 - 16:10: Integrated photodetectors: Si photodiodes in CMOS technology
- 16:10 - 17:00: Optical wireless data and power transfer systems for implants: design and implementation
Biography
Andrea De Marcellis: Andrea De Marcellis received Laurea and Ph.D. degrees from University of L'Aquila and is currently Associate Professor of Electronics at University of L'Aquila (DISIM), heading EPICS Lab and DHT Lab. His research covers mixed-signal electronic/optoelectronic ICs and systems for biomedical sensing and communication. He has coauthored a book, two book chapters, and over 170 publications.
Guido Di Patrizio Stanchieri: Guido Di Patrizio Stanchieri received Master's and Ph.D. degrees in Electronic Engineering from University of L'Aquila and is currently Assistant Professor at DISIM. His research focuses on digital electronics, integrated circuits, and data/power communication links for biomedical applications. He has coauthored one book chapter and dozens of publications.
T14 - Leveraging IEEE DataPort and IEEE Data Descriptions for Enhanced Research Impact and Student Engagement
Sunday | May 24, 2026 | 13:30 - 17:00
Abstract
This tutorial will provide an in-depth exploration of IEEE DataPort and IEEE Data Descriptions, emphasizing how to open-source datasets and write impactful academic papers. Additionally, we will discuss strategies for organizing and leveraging IEEE CAS Student Design Competitions to increase the visibility of research through the IEEE community. By attending, participants will learn how to enhance their work’s discoverability, impact, and citation potential while engaging students in research competitions.
Instructor(s)
- Yongfu Li - Shanghai Jiao Tong University, China
- Qing Zhang - Shanghai Jiao Tong University, China
Tentative Schedule
- 13:30 - 14:00: Introduction to IEEE DataPort
- 14:00 - 15:10: IEEE Data Descriptions and writing impactful papers
- 15:10 - 15:30: Coffee break
- 15:30 - 16:40: Organizing IEEE CAS Student Design Competitions
- 16:40 - 17:00: Q&A and brainstorming session
Biography
Yongfu Li: Yongfu Li (S'09-M'14-SM'18) received B.Eng. and Ph.D. degrees from NUS. He worked at GLOBALFOUNDRIES in multiple design/manufacturing roles and is currently a tenured Associate Professor in the School of Integrated Circuits, Shanghai Jiao Tong University. His research includes analog/mixed-signal circuits, biomedical signal processing, and circuit automation.
Qing Zhang: Qing Zhang received the B.S. and Ph.D. degrees from Central South University, Changsha, China, and Shanghai Jiao Tong University, Shanghai, China, in 2019 and 2026, respectively. She is currently a research fellow of Shanghai Jiao Tong University. Her research interests focus on the use of AI and shift-left methodologies in Design for Manufacturability (DFM) and Electronics Design Automation (EDA).
T15 - Modern Power Amplifier Design: From Classical Principles to AI-Assisted Optimization
Sunday | May 24, 2026 | 13:30 - 17:00
Abstract
Modern wireless and sensing systems demand power amplifiers (PAs) that
perform efficiently across an ever-widening frequency range, from
sub-GHz to sub-THz. Designing PAs over such diverse regimes is
challenging: designers must balance efficiency, linearity, and
integration constraints, all of which vary with the semiconductor
platform. CMOS, SOI, SiGe, and III-V technologies each bring different
strengths and limitations, influencing achievable performance, power
handling, and manufacturability.
This tutorial walks through PA
design from fundamentals to advanced techniques. We start with classical
PA architectures and key performance metrics at lower frequencies, then
move to millimeter-wave and sub-terahertz designs, discussing
power-combining methods, Doherty-inspired architectures, parasitic
effects, and layout considerations. Process-specific trade-offs are
highlighted, illustrated with real-world case studies that show how
design choices impact performance across different technologies and
frequency bands.
Finally, we look ahead to emerging trends and
challenges in PA design, including integration, scalability, and design
automation. By the end of the session, participants will have a clear
understanding of the frequency- and process-dependent trade-offs that
define modern PA design and practical guidance for building efficient,
high-performance amplifiers for next-generation wireless and sensing
systems.
Instructor(s)
- Prof. Xi Forest Zhu - University of Technology Sydney, Ultimo, New South Wales, Australia
- Dr. Lang Chen - Sydnicon RF Microelectronics, Suzhou, Jiangsu Province, China
Tentative Schedule
- 13:30 - 13:50: Introduction to PA Fundamentals
- 13:50 - 14:30: Power Combining Techniques for PAs
- 14:30 - 15:10: Efficiency Enhancement Techniques for PAs
- 15:10 - 15:30: Coffee break
- 15:30 - 16:30: Case Studies: practical PA implementations across technologies
- 16:30 - 17:00: Discussion and Q&A on emerging trends and future challenges
Biography
Xi Forest Zhu: Prof. Xi Forest Zhu (Senior Member, IEEE) received the B.Eng. and Ph.D. degrees in electronic engineering from the University of Hertfordshire in 2005 and 2008. He has authored/coauthored more than 150 papers. His research focuses on analog/mixed-signal and RF integrated circuits for wireless communications. He serves in multiple IEEE journal and conference roles and has been recognized among Australia's top researchers in Microelectronics.
Lang Chen: Dr. Lang Chen is co-founder and CTO of Sydnicon RF Pty Ltd. He has published high-impact papers in IEEE journals and holds 20+ patents related to power amplifier architectures and circuit techniques. He received his B.S. from UESTC, M.S. jointly from UCAS/IMECAS, and Ph.D. from the University of Technology Sydney, with research focused on power amplifier design for emerging wireless systems.
T16 - Mm-Wave to THz Signal Generation in CMOS: An Injection Locking Approach
Sunday | May 24, 2026 | 13:30 - 17:00
Abstract
Moving to higher frequencies become a consensus in communication and
radar society for wider bandwidth and smaller form factor, thereby
gestating new applications spread from mm-wave to THz frequency bands,
including 5G new radio (NR), 6G communication, automotive radar, and THz
sensing. Unlike the traditional high-frequency signal generation in
vacuum tube, which inherently has high power and low phase noise, new
demands on power, size, and cost force the signal generation to be fully
integrated on a silicon chip, but with sacrificed
performances.
In this tutorial, we focus on the fundamental
limitations of signal generation in CMOS from mm-wave to THz
frequencies, and the design trade-offs among operating frequencies,
bandwidth, phase noise, and power consumption. We will introduce new
signal generation topologies based on an injection-locking technique and
discuss the design methodology of high-frequency signal generators. This
tutorial includes discussion of fundamental problems on silicon-based
high-frequency signal generation, design of silicon-based oscillators
and phase-locked loops (PLL), introduction of the injection-locking
technique and how does it benefit for high-frequency signal generations,
design examples of mm-wave and THz injection-locked signal sources, and
their applications in communication and radar systems.
Instructor(s)
- Jingzhi Zhang - University of Electronic Science and Technology of China, China
- Xiaolong Liu - Southern University of Science and Technology, China
Tentative Schedule
- 13:30 - 15:10: Background, review of mm-wave/THz signal generation, injection-locking technique, and mm-wave implementations
- 15:10 - 15:30: Coffee break
- 15:30 - 16:30: THz injection-locked oscillators, oscillators/PLLs, conclusion and discussion
- 16:30 - 17:00: Questions and discussions
Biography
Jingzhi Zhang: Jingzhi Zhang received B.S. and Ph.D. degrees from UESTC. He was a visiting student researcher and postdoctoral scholar at Stanford University, and is currently a full Professor at UESTC. His work focuses on mm-wave frequency synthesizers, phased-array communication systems, and MIMO radar systems, with strong expertise in injection-locking circuits.
Xiaolong Liu: Xiaolong Liu received a Ph.D. from HKUST in 2019, worked as postdoctoral researcher at HKUST and in a Silicon Valley startup, and is currently Assistant Professor at SUSTech. His interests include RF, mm-wave, and sub-THz oscillators/PLLs/frequency synthesizers and transceivers in CMOS. He has developed multiple injection-locked techniques for wide locking range and low-power high-frequency ICs.
T17 - Efficient Learning-based Models for Multimodal Data Compression
Sunday | May 24, 2026 | 13:30 - 17:00
Abstract
This tutorial surveys recent advances in learning-based data compression, focusing on achieving high performance with low computational complexity. While neural compression now rivals traditional codecs, its computational cost remains a barrier to practical deployment. This tutorial is structured into two interconnected parts to address this challenge. The first part establishes a foundational understanding of state-of-the-art learned compression for images and video. Then we’ll explore efficient strategies including: (1) linear attention models (Mamba, RWKV) as alternatives of transformer and convolutions; (2) knowledge distillation for compact models; and (3) integrated restoration techniques for enhanced rate-distortion performance. The second part extends these principles to diverse modalities, covering sequential data (text, speech, tactile), multi-view representations (Gaussian Splatting, NeRF), and joint frameworks that share coding tools across data types to enable hardware savings. We conclude with key challenges and future directions for multimodal data handling and lightweight architectures.
Instructor(s)
- Li Song - Shanghai Jiao Tong University, China
- Chuanmin Jia - Peking University, China
- Zhengxue Cheng - Shanghai Jiao Tong University, China
Tentative Schedule
- 13:30 - 15:10: Comprehensive review and efficient compression models for image/video data
- 15:10 - 15:30: Coffee break
- 15:30 - 17:00: Extension to diverse data modalities in compression
Biography
Li Song: Li Song received B.E., M.S., and Ph.D. degrees from SJTU and is currently a Full Professor in Electronic Engineering. He has 300 publications, 50 granted patents, and 20 standard contributions. His interests include visual signal processing and AI for multimedia.
Chuanmin Jia: Chuanmin Jia received B.E. from Beijing University of Posts and Telecommunications and Ph.D. from Peking University. He is currently an Assistant Professor at Peking University. His research interests include intelligent video compression and multimedia signal processing, with multiple best paper and challenge awards.
Zhengxue Cheng: Zhengxue Cheng received B.E. from SJTU, M.E. from Waseda University and SJTU (double-degree), and Ph.D. from Waseda. She worked at Ant Group and is currently an assistant researcher at SJTU. Her interests include deep learning-based multimodal data compression and quality evaluation.
Tutorials Registration
For ISCAS 2026, Tutorials are FREE OF CHARGE for all registered participants. However, to manage capacity and ensure a quality experience, the following policy applies:
- Each participant can select a maximum of two tutorial sessions (one in the morning and one in the afternoon).
- Please select your preferred sessions during the online registration process.
- Participants will receive their tutorial admission tickets at the conference registration desk on-site.